The Anatomy of an Instruction Pipeline Hazard
- A case study of the B200 pipeline modelA note on methodology: Everything in this article is based on my analysis of microbenchmarks executed directly on B200 silicon.
- Nvidia does not publish instruction latencies, pipeline depths, or scoreboard encoding details for its GPUs.
- The numbers and mechanisms described here represent my best empirical understanding.
Unverified
- A case study of the B200 pipeline modelA note on methodology: Everything in this article is based on my analysis of microbenchmarks executed directly on B200 silicon.
- Nvidia does not publish instruction latencies, pipeline depths, or scoreboard encoding details for its GPUs.
- The numbers and mechanisms described here represent my best empirical understanding.
Sources: Github